Data transmission framing

ABSTRACT

Techniques for framing data in various data transmission contexts are described. A data framing technique may include a transmitter sending a data stream including repeating bits in alternating forward and reverse order. A receiver of the data stream may fold the data stream, and correlate portions of the folded data stream for purposes of validating the data stream and/or identifying an ID in the data stream. In at least some instances, once the receiver validates the data stream, the receiver may accept payload accompanying the data stream.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

The United States government has rights in this invention pursuant to Contract No. 89233218CNA000001 between the United States Department of Energy (DOE), the National Nuclear Security Administration (NNSA), and Triad National Security, LLC for the operation of Los Alamos National Laboratory.

BACKGROUND

In some communications systems, data is transmitted as a continuous sequence of bits. Data reception, in these systems, includes determining the values of individual bits as well as grouping the individual bits into “frames.”

In American Standard Code for Information Interchange (ASCII), which is a character encoding standard for electronic communication, framing data may include splitting 8-bits of one ASCII character from bits of the next ASCII character. This includes “frame synchronization,” which is the determination of which bit in a sequence corresponds to the first bit of a frame.

For example, in ASCII, “a” equals 01100001, “b” equals 01100010, and so on. Thus, a continuous sequence of “ . . . ababab . . . ” equals . . . 011000010110001001100001011000100110000101100010 . . . . But, if the receiver starts at the sixth bit, for example, the signal looks like . . . 0010110001001100001011000100110000101100010 . . . . This leads to a determined continuous sequence of 00101100 and 01001100 bytes, which represent “,” and “L,” respectively (not “a” and “b” as transmitted).

Framing in ASCII may be indicated by inserting non-information bits into a continuous sequence of bits. For example, an individual 8-bit character may be preceded by a start bit (e.g., 0) and followed by a stop bit (e.g., 1), thereby expanding the 8-bit symbol to a 10-bit symbol. The correct framing may be found automatically after a few characters because incorrect framing does not match the values of the corresponding start and stop bits of 0 and 1 reliably.

An Extremely Low-Resource Optical Identifier (ELROI) beacon is a concept for an optical license plate that can provide unique identifier (ID) numbers for anything that goes into space. In an ELROI ID signal, flashes of light are a strictly-periodic sequence of clock ticks where a flash represents a “1” and a non-flash represents a “0.” This pattern repeats every n clocks (e.g., n=127 for purposes of the following example), and the n-bit number thus represented is drawn from an alphabet of spacecraft IDs. If there is no framing mechanism, then each ID number can be read in any of n different ways, corresponding to an arbitrary choice of which bit in the data stream is the first bit, effectively requiring an alphabet of spacecraft IDs to be n times as large. The logarithm of the size of the alphabet corresponds to how much information (e.g., number of information bits when the logarithm is base-2) may be transmitted in the n bits of the ID code. The excess of n above the number of information bits can be used for error correction and other purposes, allowing consequent increased reliability at lower power levels over a noisy channel. Taking a nominal million available IDs, which represents 20 bits of information (log_2(1,000,000)˜20), 127 million rotated IDs must be reserved (i.e., each basic ID number must also be represented by the rotated version where the first m bits are taken off the front and moved to the back, for m=0 . . . 126). This requires 27 bits of information to be transmitted (log_2(127,000,000)˜27, effectively 20 bits of ID plus 7 bits of rotation information). The rotation information is effectively useless, as it is solely an indication of at what clock cycle the reading started, leading to a waste of 7/27 (˜26%) of the information.

Code Division Multiple Access (CDMA) is a channel access method used by various radio communication technologies. In CDMA, a single symbol of information can be encoded as a pattern of chips, each of which is an elementary bit that is individually too weak to read reliably. A symbol might be n chips long, with the following symbol occupying the subsequent n chips, and so on. A “1” symbol might be a specific pattern of chips while the “0” symbol might be the pattern with each elementary bit replaced by its inverse. A framing problem in the CDMA context involves determining which chip (out of n chips) is the first chip in a symbol.

Framing techniques of the foregoing communication technologies unnecessarily use up bandwidth.

SUMMARY

The present disclosure provides improved techniques for framing data in various data transmission contexts. A data framing technique of the present disclosure includes sending consecutive transmissions of a data stream in alternating forward and reverse order. This enables a framing clock to be recovered without loss of communications bandwidth inherent in known techniques.

A transmitter may generate and send a data stream including repeating bits in alternating forward and reverse order. A receiver of the data stream may fold the data stream, and correlate portions of the folded data stream for purposes of validating the data stream and/or identifying an ID in the data stream. In at least some instances, once the receiver validates the data stream, the receiver may accept payload accompanying the data stream.

Teachings of the present disclosure may be used in binary communications systems (e.g., involving data streams of 0 and 1 values). Teachings of the present disclosure may also or alternatively be used in non-binary communications systems, such as Quadrature Amplitude Modulation (QAM), where unit symbols have more than 2 values.

An aspect of the present disclosure relates to a data transmitter comprising first circuitry configured to transmit a stream of data including repeating alternating instances of a first data portion in a forward order and a second data portion representing a reverse order of the first data portion. In at least some examples, the first data portion comprises 127 bits. In at least some examples, the stream comprises a 0 or 1 bit between the first and second data portions. In at least some examples, the first data portion is located previous and adjacent to the second data portion in the stream. In at least some examples, the first data portion is located subsequent and adjacent to the second data portion in the stream. In at least some examples, a first repeating alternating instance of the first and second data portions comprises 255 bits. In at least some examples, the second data portion comprises an inverted representation of the reverse order of the first data portion. In at least some examples, the inverted representation encodes the stream.

Another aspect of the present disclosure relates to a data receiver comprising circuitry configured to receive a stream of data including repeating alternating instances of a first data portion in a forward order and a second data portion representing a reverse order of the first data portion, and correlate the first data portion with the second data portion. In at least some examples, the circuitry is further configured to identify a palindrome sequence using the stream. In at least some examples, the first data portion comprises 127 bits. In at least some examples, the stream comprises a 0 or 1 bit between the first and second data portions. In at least some examples, the first data portion is located previous and adjacent to the second data portion in the stream. In at least some examples, the first data portion is located subsequent and adjacent to the second data portion in the stream. In at least some examples, a first repeating alternating instance of the first and second data portions comprises 255 bits. In at least some examples, the data receiver accepts payload after correlating the first data portion with the second data portion. In at least some examples, the circuitry is further configured to correlate the first data portion with the second data portion in a shift register. In at least some examples, the shift register comprises a fold point, and the circuitry comprises a XNOR gate configured to compare bits one position way from the fold point. In at least some examples, the second data portion comprises an inverted representation of the reverse order of the first data portion. In at least some examples, the inverted representation encodes the stream.

BRIEF DESCRIPTION OF DRAWINGS

For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.

FIG. 1 is a conceptual diagram illustrating a system configured to frame data according to embodiments of the present disclosure.

FIG. 2 is a conceptual diagram illustrating an example hardware-based implementation in which a receiver may process a data stream using a shift register.

FIG. 3 is a conceptual diagram illustrating an Extremely Low-Resource Optical Identifier (ELROI) data stream including repeating bits in alternating forward and reverse order according to embodiments of the present disclosure.

FIG. 4 is a conceptual diagram illustrating a Code Division Multiple Access (CDMA) data stream including repeating bits in alternating forward and reverse order according to embodiments of the present disclosure.

FIG. 5 is a block diagram conceptually illustrating example components of a transmitter according to embodiments of the present disclosure.

FIG. 6 is a block diagram conceptually illustrating example components of a receiver according to embodiments of the present disclosure.

DETAILED DESCRIPTION

The present disclosure provides techniques for framing data in various data transmission contexts. A data framing technique of the present disclosure includes sending a data stream including repeating bits in alternating forward and reverse order. Teachings of the present disclosure may be used in binary communications systems (e.g., involving data streams of 0 and 1 values). Teachings of the present disclosure may also or alternatively be used in non-binary communications systems, such as Quadrature Amplitude Modulation (QAM), where unit symbols have more than 2 values.

As illustrated in FIG. 1, a transmitter 110 may send a data stream 105 to a receiver 120. The data stream 105 may include sequences of bits that are repeated in alternating forward and reverse orders (as illustrated in FIG. 2).

In the Extremely Low-Resource Optical Identifier (ELROI) context, for example, the transmitter 110 may be an optical beacon, which transmits flashes of light, attached to an object outside of the Earth's atmosphere, and the receiver 120 may be a computing device including an optical detector, configured to detect flashes of light, attached to a telescope located on or near the Earth's surface. In the Code Division Multiple Access (CDMA) context, the transmitter 110 and/or receiver 120 may be a global positioning system (GPS) device, a mobile phone, and a satellite, or some other device that communicates through CDMA protocols.

Embodiments of the present disclosure may be implemented using hardware, firmware, software, or any suitable combination of hardware, firmware, and/or software. FIG. 2 shows an example of a hardware-based implementation of possible components within the receiver 120. Although the specific example shown in FIG. 2 is hardware-based, it should be appreciated that the functionality of the illustrated components for comparing sequences of bits, etc., could alternatively be implemented using software and/or firmware in addition to or in lieu of hardware.

The receiver 120 may process the data stream 105 as illustrated in FIG. 2. For example, the receiver 120 may implement a shift register 210 into which the data stream 105 is fed one bit at a time. The shift register 210 may, for example, be a first-in/first-out component such that a bit is moved an additional spot in the shift register 210 each time a new bit is added to the shift register 210. In other words, a first received bit is initially placed in a first position of the shift register 210. When a second bit is received, the first bit is moved to a second position of the shift register 210 and the second bit is placed in the first position of the shift register 210, and so on.

In the illustrated hardware implementation, the receiver 120 may include a fold point 220 corresponding to a particular position within the shift register 210. As shown, the receiver 120 may, for example, implement XNOR gates 230 that compare respective pairs of bits on either side of the fold point 220. An XNOR gate produces a “true” output when all inputs to the XNOR gate are “true” or when all inputs to the XNOR gate are “false.” In other words, an XNOR gate produces a true output when all inputs to the XNOR gate are equivalent. Table 1 below illustrates potential outputs of an XNOR gate configured to receive 2 inputs.

TABLE 1 Potential outputs of an XNOR gate configured to receive 2 inputs. Input A Input B Output 0 0 1 0 1 0 1 0 0 1 1 1

Referring to FIG. 2, in an example, a first XNOR gate 230 a may compare bits that are one position away from the fold point 220, a second XNOR gate 230 b may compare bits that are two positions away from the fold point 220, and so on. The number of XNOR gates 230 implemented by the receiver 120 may depend on the amount of bits to be compared by the receiver 120. Thus, receivers 120 according to the present disclosure may have different numbers of XNOR gates 230.

Outputs of the XNOR gates 230 may be fed into an AND gate 240. While FIG. 2 illustrates the AND gate 240 being configured to receive outputs from two XNOR gates 230, one skilled in the art will appreciate that the AND gate 240 may be configured to receive an output from each XNOR gate 240 implemented by the receiver 120. A receiver 120 may implement a single AND gate 240, or more than one AND gate 240, to effect the desired AND operation.

An AND gate provides a true output when all the inputs to the AND gate are true. In other words, an AND gate produces a true output when all XNOR gates, feeding into the AND gate, produce true outputs. Table 2 below illustrates potential outputs of an AND gate configured to receive 2 inputs.

TABLE 2 Potential outputs of an AND gate configured to receive 2 inputs. Input A Input B Output 0 0 0 0 1 0 1 0 0 1 1 1

The AND gate 240 processes the output of each XNOR gate 230 to determine if the bits on each side of the fold point 220 are correlated. For example, the bits may be considered correlated if the bits one position from the fold point 220 match, the bits two positions from the fold point 220 match, and so on. In at least some configurations, the AND gate 240 may be configured to process at least a threshold number of XNOR gate 230 outputs. By implementing a threshold, the receiver 120 is able to minimize false correlations (e.g., recognition of correlated bits near the fold point 220, but bits further from the fold point 220 would not be correlated if further XNOR gates were implemented).

If the AND gate 240 produces an output representing the data is correlated about the fold point 220 (e.g., produces a true output), the receiver 120 may be considered to have recognized a palindromic sequence in the data stream 105. A palindromic sequence is a sequence whereby reading a data sequence in a forward order matches reading a data sequence in a reverse order. With reference to data stream 105 represented in FIG. 2, a palindromic sequence may be recognized if, for example, the fold point 220 is located between a sequence of forward bits and a sequence of reverse bits. If the receiver 120 successfully correlates the bits about the fold point 220, in at least some instances, the receiver 120 may then accept an appropriate number of bits on one side of the fold point as a payload corresponding to a desired sequence of bits.

In some implementations, the receiver 120 may implement one or more XOR gates rather than XNOR gates. An XOR gate produces a true output when the number of true inputs is odd. In other words, an XOR gate produces a true output when the inputs to the XOR gate are not equivalent. Table 3 below illustrates potential outputs of an XOR gate configured to receive 2 inputs.

TABLE 3 Potential outputs of an XOR gate configured to receive 2 inputs. Input A Input B Output 0 0 0 0 1 1 1 0 1 1 1 0

The receiver 120 may implement one or more XOR gates in lieu of the XNOR gates 230 shown in FIG. 2, for example, if the transmitter 110 is configured to invert the bits of the “reverse order” portions of the alternating forward and reverse order bit sequences. Equivalently, the receiver 120 may implement a NOR gate 250 in lieu of the AND gate 240. Such inverting may, for example, create a “balanced” data stream that includes an approximately equal number of ones and zeros. Depending on the application, a receiver 120 may include either or both of the AND gate 240 or the NOR gate 250. One skilled in the art will appreciate that correlations calculations described herein may be used to perform anti-correlation calculations through use of the NOR gate 250. Table 4 below illustrates potential outputs of a NOR gate configured to receive 2 inputs.

TABLE 4 Potential outputs of a NOR gate configured to receive 2 inputs. Input A Input B Output 0 0 1 0 1 0 1 0 0 1 1 0

As noted above, in addition to or in lieu of hardware, the functionality of the receiver 120 may be implemented using software and/or firmware. For example, in some embodiments, the receiver 120 may store the data stream 105 to memory, and may perform correlation processing about various fold points within the stored data sequence until palindromic sequences of data on either side of such fold points are identified. In some implementations, the fold point that corresponds to each identified palindromic sequence greater than a threshold length may be determined to correspond to a frame clock.

The receiver 120 may not select an appropriate fold point 220 in the first instance. That is, the receiver 120 may initially select a fold point 220 that does not result in the data being correlated on either side. When this occurs, the receiver 120 may move the fold point 220 to a different position within the stored data stream, and may then process the data stream about the new fold point 220. The receiver 120 may move the fold point 220, and perform the correlation processing described above, with respect to each fold point until the data is correlated or until the receiver 120 has performed correlation processing with respect to at least a threshold number of fold points. If the receiver 120 successfully correlates the bits of the data stream 105, in at least some instances, the receiver 120 may then accept an appropriate number of bits on one side of the fold point resulting in such a correlation as a payload.

For communicating over a noisy channel, the above described gates may be replaced with non-binary analogs to improve the probability of accurately detecting the fold point. For example, the XNOR gates 230 can be replaced by arithmetic function units calculating:

P(A=0)*P(B=0)+P(A=1)*P(B=1)

where P(A=0) is the probability that input A corresponds to a zero bit, P(B=0) is the probability that input B corresponds to a zero bit, P(A=1) is the probability that input A corresponds to a 1 bit, and P(B=1) is the probability that input B corresponds to a 1 bit. The AND gate 240 can be replaced by an adder arithmetic function unit that calculates the sum of its inputs. The fold point is most likely to correspond to the shift that has the maximum output value of the adder arithmetic function unit.

The above described data framing techniques may be implemented, for example, in Extremely Low-Resource Optical Identifier (ELROI) communications systems. In an ELROI communications system, an optical license plate can be provided by unique identifier (ID) numbers for anything that goes into space. In an ELROI ID signal, flashes of light are a strictly-periodic sequence of clock ticks where a flash represents a “1” and a non-flash represents a “0.” This pattern repeats every n clocks, and the n-bit number thus represented is drawn from an alphabet of spacecraft IDs.

For an ELROI communications system, instead of transmitting a 127-bit ID (or some other n-bit ID) over and over (as performed by known techniques), a data stream may repeat the ID in forward and reverse order (as illustrated in FIG. 3). This data stream includes an “IDDI” palindrome sequence. In an ELROI communications system, the palindrome sequence may be 254 bits long.

After each “IDDI” sequence, a “0” may be added (as illustrated in FIG. 3). This produces a repetition sequence of 255 bits long. The 0 may be added as an indicator to the receiver 120 of where the first bit of a forward “ID” is located. One skilled in the art will appreciate that the 0 bit does not need to be added between a reverse ID and a forward ID when correlation, but not direction, of bits is important.

The foregoing ELROI framing technique provides a framing solution with minimal additional bandwidth needed. The signal power remains (e.g., taking only 1 extra bit time every 254 bits to transmit).

The framing techniques of the present disclosure may be implemented, for example, in Code Division Multiple Access (CDMA) communications systems. A CDMA communications system is a multi-access system that permits numerous transmitters to send information simultaneously over a single communication channel. CDMA communications systems include global positioning systems (GPSs), mobile phone networks, and satellite communications systems. Data to be transmitted is combined with a pseudo-random code. The pseudo-random code may be a string of binary bits.

A CDMA communications system implementing the presently disclosed framing techniques may transmit the pseudo-random bits in repeating forward and reverse order, with the bits inverted or not to encode data ones and zeros (as illustrated in FIG. 4). A receiver 120 of the CDMA data stream may correlate (and anti-correlate) the data about a fold point. From this correlation, the code may be validated by the receiver 120 and the receiver 120 may, thereafter, accept accompanying payload.

FIG. 5 is a block diagram conceptually illustrating the transmitter 110 according to the present disclosure. FIG. 6 is a block diagram conceptually illustrating the receiver 120 according to the present disclosure.

Each of these devices (110/120) may include one or more controllers/processors (504/604), which may each include a central processing unit (CPU) for processing data and computer-readable instructions, and memory (506/606) for storing data and instructions of the respective device. The memories (506/606) may individually include volatile random access memory (RAM), non-volatile read only memory (ROM), non-volatile magnetoresistive memory (MRAM), and/or other types of memory. Each device (110/120) may also include a data storage component (508/608) for storing data and controller/processor-executable instructions. Each data storage component (508/608) may individually include one or more non-volatile storage types such as magnetic storage, optical storage, solid-state storage, etc. Each device (110/120) may also be connected to removable or external non-volatile memory and/or storage (such as a removable memory card, memory key drive, networked storage, etc.) through respective input/output device interfaces (502/602).

Computer instructions for operating each device (110/120) and its various components may be executed by the respective device's controller(s)/processor(s) (504/604), using the memory (506/606) as temporary “working” storage at runtime. A device's computer instructions may be stored in a non-transitory manner in non-volatile memory (506/606), storage (508/608), or an external device(s). Alternatively, some or all of the executable instructions may be embedded in hardware or firmware on the respective device in addition to or instead of software.

Each device (110/120) includes input/output device interfaces (502/602). A variety of components may be connected through the input/output device interfaces (502/602). Additionally, each device (110/120) may include an address/data bus (524/624) for conveying data among components of the respective device. Each component within a device (110/120) may also be directly connected to other components in addition to (or instead of) being connected to other components across the bus (524/624).

Via the input/output device interfaces (502/602), the devices (110/120) may send and receive data. Such data transmission and/or receipt may utilize wireless local area network (WLAN) (such as WiFi) communications, Bluetooth communications, satellite communications, wireless network radio communications (such as a radio capable of communication with a wireless communication network such as a Long Term Evolution (LTE) network, WiMAX network, 3G network, 4G network, 5G network, etc.), or some other communications modality presently or not yet known. A wired connection, such as Ethernet, may also be supported.

Referring to FIG. 5, the transmitter 110 may include a data stream generation component 510. The data stream generation component 510 may be configured to generate a data stream including repeating bits in alternating forward and reverse order. The data stream generation component 510 may also be configured to associate a data stream with payload, in at least some instances.

The transmitter 110 may include an optical transmitter 512 configured to transmit optical signals. Many optical signal transmitting devices are known in the art. The optical transmitter 512 may be an art known device and one skilled in the art will appreciate which art known optical signal transmitting device to implement in a given scenario.

The transmitter 110 may include a radio frequency (RF) transmitter 514 configured to transmit RF signals. Many RF signal transmitting devices are known in the art. The RF transmitter 514 may be an art known device and one skilled in the art will appreciate which art known RF signal transmitting device to implement in a given scenario.

Referring to FIG. 6, the receiver 120 may include a data stream processing component 610. The data stream processing component 610 may be configured to correlate portions of data streams for purposes of validating the data streams and/or identifying IDs in the data streams.

The receiver 120 may include an optical receiver 612 configured to receive/detect optical signals. Many optical signal receiving/detecting devices are known in the art. The optical receiver 612 may be an art known device and one skilled in the art will appreciate which art known optical signal receiving/detecting device to implement in a given scenario.

The receiver 120 may include a RF receiver 614 configured to receive/detect RF signals. Many RF signal receiving/detecting devices are known in the art. The RF receiver 614 may be an art known device and one skilled in the art will appreciate which art known RF signal receiving/detecting device to implement in a given scenario.

The concepts disclosed herein may be applied within a number of different devices and computer systems.

The above aspects of the present disclosure are meant to be illustrative. Many modifications and variations of the disclosed aspects may be apparent to those of skill in the art. Persons having ordinary skill in the field of computers and data transmissions should recognize that components and process steps described herein may be interchangeable with other components or steps, or combinations of components or steps, and still achieve the benefits and advantages of the present disclosure. Moreover, it should be apparent to one skilled in the art, that the disclosure may be practiced without some or all of the specific details and steps disclosed herein.

Aspects of the disclosure may be implemented as a computer method or as an article of manufacture such as a memory device or non-transitory computer readable storage medium. The computer readable storage medium may be readable by a computer and may comprise instructions for causing a computer or other device to perform processes described in the present disclosure. The computer readable storage medium may be implemented by a volatile computer memory, non-volatile computer memory, hard drive, solid-state memory, flash drive, removable disk, and/or other media. In addition, components of system may be implemented as in firmware or hardware.

Conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or steps. Thus, such conditional language is not generally intended to imply that features, elements, and/or steps are in any way required for one or more embodiments. The terms “comprising,” “including,” “having,” and the like are synonymous and are used inclusively, in an open-ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. Also, the term “or” is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list.

Disjunctive language such as the phrase “at least one of X, Y, Z,” unless specifically stated otherwise, is understood with the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present.

As used in this disclosure, the term “a” or “one” may include one or more items unless specifically stated otherwise. Further, the phrase “based on” is intended to mean “based at least in part on” unless specifically stated otherwise.

While the present disclosure has been particularly described in conjunction with specific embodiments, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications, and variations as falling within the true spirit and scope of the present disclosure. 

What is claimed is:
 1. A data transmitter, comprising: first circuitry configured to transmit a stream of data including repeating alternating instances of a first data portion in a forward order and a second data portion representing a reverse order of the first data portion.
 2. The data transmitter of claim 1, wherein the first data portion comprises 127 bits.
 3. The data transmitter of claim 1, wherein the stream comprises a 0 or 1 bit between the first and second data portions.
 4. The data transmitter of claim 3, wherein the first data portion is located previous and adjacent to the second data portion in the stream.
 5. The data transmitter of claim 3, wherein the first data portion is located subsequent and adjacent to the second data portion in the stream.
 6. The data transmitter of claim 3, wherein a first repeating alternating instance of the first and second data portions comprises 255 bits.
 7. The data transmitter of claim 1, wherein the second data portion comprises an inverted representation of the reverse order of the first data portion.
 8. The data transmitter of claim 7, wherein the inverted representation encodes the stream.
 9. A data receiver, comprising: circuitry configured to receive a stream of data including repeating alternating instances of a first data portion in a forward order and a second data portion representing a reverse order of the first data portion, and correlate the first data portion with the second data portion.
 10. The data receiver of claim 9 wherein the circuitry is further configured to: identify a palindrome sequence using the stream.
 11. The data receiver of claim 9, wherein the first data portion comprises 127 bits.
 12. The data receiver of claim 9, wherein the stream comprises a 0 or 1 bit between the first and second data portions.
 13. The data receiver of claim 12, wherein the first data portion is located previous and adjacent to the second data portion in the stream.
 14. The data receiver of claim 12, wherein the first data portion is located subsequent and adjacent to the second data portion in the stream.
 15. The data receiver of claim 12, wherein a first repeating alternating instance of the first and second data portions comprises 255 bits.
 16. The data receiver of claim 9, wherein the data receiver accepts payload after correlating the first data portion with the second data portion.
 17. The data receiver of claim 9, wherein the circuitry is further configured to: correlate the first data portion with the second data portion in a shift register.
 18. The data receiver of claim 17, wherein: the shift register comprises a fold point; and the circuitry comprises a XNOR gate configured to compare bits one position way from the fold point.
 19. The data receiver of claim 9, wherein the second data portion comprises an inverted representation of the reverse order of the first data portion.
 20. The data receiver of claim 19, wherein the inverted representation encodes the stream. 